FIG. 1 is an illustration of a CMOS active pixel sensor (APS) imaging system 100. The system 100 includes a pixel array 110, shown in FIG. 3 as including a row decoder 112 and a plurality of pixels P arranged into an array 111 having N rows and M columns. If system 100 is a color system, the pixels P would be made sensitive to the primary colors of red, green, or blue, and would typically be arranged in a Bayer pattern in which alternating rows are comprised of alternating green and red pixels and alternating blue and green pixels, respectively.
FIG. 2 illustrates one exemplary architecture for a pixel P. The pixel P includes a photosensitive element, such as photodiode 210, which converts optical energy into an electrical signal. The photodiode 210 is coupled to node-A, which is also coupled to a source/drain terminal of transistor 220. The transistor 220 has another source/drain terminal coupled to a Vdd potential source and a gate coupled to receive a read signal. Node-A is coupled to the gate of a source following transistor 230, which has one source/drain terminal coupled to the Vdd potential source and another source/drain terminal coupled to a source/drain terminal of a row transistor 240. The row transistor 240 has its gate coupled to a ROW control signal, and its other source/drain terminal coupled to an output line 250 at node-B.
The pixel P produces a voltage at node-A related to the brightness of the light sensed by the photosensitive element 210. The voltage at node-A controls the output at node-B by controlling the gate of the source following transistor 230. A row transistor 240 controls, via the ROW signal on line 260, whether the output of the source follower transistor 230 is coupled to the output line 250 at node-B. The output line 250 is also coupled to other pixels P in the array 110 having the same column position but in different rows of the array. It should be noted that the illustrated pixel P is only one exemplary architecture of a pixel. As is well known, there are several different architectures suitable for pixels, including those which utilize, for example, reset transistors and output a differential signal comprising a photo signal component and a reset signal component.
Referring back to FIG. 1, the electrical signal output by the pixel P are analog signals. These signals are subsequently processed and digitized by either analog processing and digitization circuit (bottom) 120b or analog processing and digitization circuit (top) 120t. The circuits 120b, 120t convert the analog signal into an equivalent digital signal and conveys the digital signal, via data bus 181, to a digital processing and storage system 130, for further processing in the digital domain (e.g., color interpolation) and storage. A control circuit 140 coordinates the activities of the pixel array 110, analog processing and digitization systems 120b, 120t, and digital processing and storage system 140 via control bus 182.
FIG. 3 is a more detailed diagram of the pixel array 110 and the analog processing and digitization systems 120b, 120t. The pixel array 110 includes an array 111 of pixels P and a row decoder 112. The row decoder 112 receives a row address from, for example, control circuit 140 on signal line 113. The row decoder 112 decodes the row address and activates one row of the array 111 by driving one of the signal lines 260 to a high logic state while maintaining the other signal lines 260 at a low logical state.
Each analog processing and digitizing circuit 120b, 120t is contain a plurality of sample-and-hold circuits 121 and an analog-to-digital converters 123. The sample-and-hold circuits 121 are each coupled to a respective column output line 250 of the pixel array. More specifically, the sample-and-hold circuits 121 in the bottom circuit 120b are coupled, via lines 250, to odd numbered columns while the sample-and-hold circuits 121 in the top circuit 120t are coupled, via lines 250, to even numbered columns. Each sample-and-hold circuit 121 is also coupled to signal line 122b (for bottom circuit 120b) or 122t (for top circuit 120t) for receiving control signals SHEb and SHEt, respectively.
The state of control signal SHEb and SHEt determines when the sample-and-hold circuits 121 sample and hold their input signals.
Each sample-and-hold circuit 121 is associated with a corresponding analog-to-digital converter 123. Each analog-to-digital converter 123 accepts as its input, the signal output by a respective sample-and-hold circuit 121. Each analog-to-digital converter 123 accepts, on signal line 124b (for bottom circuit 120b) or signal line 124t (for top circuit 120t), control signals ADEb, ADEt, respectively, for determining when to perform the analog to digital conversion.
Now also referring to FIG. 4, the operation of the pixel array 110 and the top and bottom analog processing and digitizing circuits 120b, 120t can be explained. The process begins when the row decoder 111 decodes a row address previously supplied on signal line 112 by setting one of the signal lines 260 to a high logical state and setting the other signal lines 260 to a low logical state. This is reflected in FIG. 4 by the ROW signal going high for “row i.” As previously explained with respect to FIG. 2, enabling the ROW signal also causes the output of the pixel P to be coupled to output lines 250. Thus, pixels P corresponding to odd numbered columns in row i have their outputs coupled to corresponding sample-and-hold circuit 121 (at bottom circuit 120b), while pixels P corresponding to even numbered columns in row i have their outputs coupled to corresponding sample-and-hold circuits 121 (at top circuit 120t).
The top 120t and bottom 120b circuits cooperate and simultaneously process a single row. The signals SHEb and SHEt, which were low, go high simultaneously with the ROW signal going high. This enables the sample-and-hold circuits 121 in the bottom and top circuits 120b to sample-and-hold their corresponding pixels signals.
The signals SHEb and SHEt then are brought low. At this point the sample-and-hold circuits have buffered the pixel output and make available the buffered signal to the analog-to-digital converters 124.
Shortly thereafter, the ADEb and ADEt signals, which were low, go high. This enables the analog-to-digital converters 124 in the bottom and top circuits 120b, 120t. The buffered signals in the sample-and-hold circuits 121 for both odd and even pixels are converted into a digital signal. The ADEb and ADEt signals then go back low.
As the digital data is made available to the digital processing and storage system 130 (signified on FIG. 4 by the “row i” on signal line DATA), the process repeats with the next row in the array (i.e., row i+1) as indicated by the ROW signal going high for row i+1. This process is repeated until each row in the array has been thus processed. At this point, each pixel P in the array 110 has been processed and the process may be repeated for another image frame.
The above described apparatus and method therefore provides for a high speed mechanism for converting the analog signal output by each pixel P in the array 110 into a digital signal, where it can be digitally processed and stored by the digital processing and storage system 130. However, some applications, such as high speed photography, slow motion filming, or even information retrieval from a holographic memory system require faster pixel digitization. Accordingly, there is a need and desire for high speed architecture for performing digitization in an imaging system.